In a memory device it is desirable to read and write data in the fastest manner possible while using the least amount of current or power as possible. As such, multiple bytes of data are often written to or read from one memory device to another memory device during a single operation. For example, during a write operation the data bits which are charged can draw current from the memory device while the data is stored. Thus, the more bits associated with the data that are set (e.g., charged having a value of “1”), the more power expended by the memory device during the write operation. However, it will be readily appreciated by those skilled in the art that some technology, which permits the programming of bits which are not set, such as NAND memory, can draw current during a write operation for bits that are not set (e.g., having a value of “0”).
With the recent explosion in consumer demand for miniaturized portable devices (e.g., digital cameras, portable audio players, personal digital assistants, digital phones, and the like), the ability to efficiently program data in these devices and to minimize the power usage associated with these devices are of increasing importance. This is particularly important in flash memory devices, where the performance speed of the flash memory is adversely affected by the availability of an adequate power supply during write operations. Flash memories include arrays of flash cells, or transistors, that are electrically programmed using relatively high drain and gate bias voltages. However, designers of electrical systems that incorporate flash memories prefer not to include high voltage supplies in the electrical systems in order to reduce electrical system cost and power consumption. As a result, flash memories are designed for use with low voltage supplies having voltages, for example, as low as three volts.
Flash write operations require a relatively substantial current. For example, it is common to use 500 microamps per memory cell during a write operation. A two-byte write operation, therefore, requires 8 milliamps of current at a six-volt power supply. This power is not a major concern where an external Vpp supply is available. However, in low voltage memory devices the availability of this external supply is often eliminated. Thus, the flash memories are also designed to include charge pumps to create the required higher Vpp supply voltages. In addition, internal Vpp supply generators or charge pumps are limited, primarily due to economic reasons, in the amount of current which can be provided during write operations.
Conventional charge pumps can simultaneously program only relatively few flash cells. The number of memory cells, therefore, written during one write cycle is reduced into segments. One typical 16-bit programming operation is performed 4 bits, rather than 16 bits, at a time. This segmented programming operation significantly increases the programming time of flash memories. For example, a flash memory which is specified to operate a three volt power supply may be limited to writing 4 bits of data at once. To write two bytes of data, four separate write operations are required. Similarly, a flash memory which is specified to operate at six volts may be limited to writing one byte of data at once.
To reduce the current associated with programming memory, the bits associated with the data may be buffered into packets and stored in a volatile memory storage within the memory device. Next, the packets in the volatile memory are interrogated to determine the total number of set bits within each packet. If the total set bits within a packet exceeds more than half the total bits contained within the packet, then the packet is inverted before it is programmed or transferred to a non volatile storage associated with the memory device. In this way, the current draw is reduced during the write operation. However, each data packet is passed over twice, namely with a first pass that buffers the packet in a volatile storage and then with a second pass that evaluates the packet to determine whether or not an inversion on the packet needs to occur. Accordingly, the process requires excess current to perform the second pass and it further creates unnecessary latency during the data transfer.
Alternatively, some memory devices elect not to buffer the data as it is transferred from a source to a target (e.g., non volatile storage). This reduces the need for a volatile storage during the data transfer, but does not necessarily increase the performance associated with the data transfer since, as will be apparent to those skilled in the art, if the data being transferred has more than half of its data bits set, then the current draw will be increased to perform the storage in the non volatile storage. Correspondingly, memory devices which do not buffer the data during a data transfer consume greater amounts of power.
As is readily apparent any improvements, associated with the transfer speed and the current draw occurring during a data transfer to a non volatile storage in a memory device, is highly desirable and significant. Memory devices continue to be miniaturized requiring sub-lithographic dimensions of the electromechanical structures comprising the devices. At the same time, these devices are performing more complex operations and demanding less power.
Therefore, there is a need to reduce the data transfer time occurring within a memory device, particularly a flash memory device. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device which can operate using a low voltage supply having an increased data transfer throughput during data transfer operations.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate implementations.